LTC6954IUFF-1#TRPBF Price|Datasheet

LTC6954IUFF-1#TRPBF

IC CLK BUFFER 1:3 1.8GHZ

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In Stock

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Shenzhen: 1730 pcs

Shanghai: 8133 pcs

Hong Kong: 1154 pcs

United States: 5058 pcs

The above prices and inventory are for reference only, please consult customer service for the latest quotation and inventory!

Specifications of LTC6954IUFF-1#TRPBF

Part Number	LTC6954IUFF-1#TRPBF
Date Code	2352
Quantity Available	16075 pcs
Manufacturer	Linear Technology/Analog Devices
Lead Time	Ship within 24 hours
QTY	3000
Datasheet	LTC6954.pdf
Minimum Quantity	More than 50pcs
Distributor	SingSun
RoHS Status	Lead free / RoHS Compliant
Ship From	Hong Kong
Shipment Way	EMS/SF/DHL/TNT/UPS/FedEx
Country of Assembly	MALAYSIA
Country of Diffusion	KOREA
Lot Number	QR73344.86

Base Product Number	LTC6954
Packaging	Tape & Reel (TR)
MSL	1
Type	Fanout Buffer (Distribution), Divider
Number of Circuits	1
Ratio - Input:Output	1:03
Differential - Input:Output	Yes/Yes
Input	LVCMOS, LVDS, LVPECL
Output	LVPECL
Frequency - Max	1.8GHz
Voltage - Supply	3.15 V ~ 3.45 V
Operating Temperature	-40°C ~ 105°C
Mounting Type	Surface Mount
Package / Case	36-WFQFN Exposed Pad
Supplier Device Package	36-QFN (4x7)

LTC6954IUFF-1#TRPBF Features

● Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking
● Additive Jitter < 20fs_RMS (12kHz to 20MHz)
● Additive Jitter < 85fs_RMS (10Hz to Nyquist)
● 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0)
● 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4)
● EZSync™ Clock Synchronization Compatible
● Three Independent, Low Noise Outputs
● Four Output Combinations Available
● Three Independent Programmable Dividers Covering All Integers From 1 to 63
● Three Independent Programmable Delays Covering All Integers From 0 to 63
● –40°C to 105°C Junction Temperature Range

LTC6954IUFF-1#TRPBF Description

The LTC6954IUFF-1#TRPBF is a family of very low phase noise clock distribution parts. Each part has three outputs and each output has an individually programmable frequency divider and delay. There are four members of the family, differing in their output logic signal type:

LTC6954-1: Three LVPECL outputs

Each output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output.

The LTC6954 also features Linear Technology’s EZSync system for perfect clock synchronization and alignment every time.

All device settings are controlled through an SPI-compatible serial port.

LTC6954IUFF-1#TRPBF Tags

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