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LTC6950IUHH

LTC6950IUHH

IC POWER MANAGEMENT

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Shenzhen
733 pcs
Shanghai
845 pcs
Hong Kong
8168 pcs
United States
6224 pcs
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Specifications of LTC6950IUHH

Part Number LTC6950IUHH
Date Code 2327
Quantity Available 15970 pcs
Manufacturer Linear Technology/Analog Devices
Lead Time Ship within 24 hours
QTY 2500
Datasheet LTC6950.pdf
Minimum Quantity More than 50pcs
Distributor SingSun
RoHS Status Lead free / RoHS Compliant
Ship From Hong Kong
Shipment Way EMS/SF/DHL/TNT/UPS/FedEx
Country of Assembly PHILIPPINES
Country of Diffusion IRELAND
Lot Number MZ42845.12
MSL 1
Base Product Number LTC6950
Packaging Tube
Type Clock/Frequency Synthesizer, Fanout Buffer (Distribution)
PLL Yes
Input Clock
Output CMOS, LVDS, PECL
Number of Circuits 1
Ratio - Input:Output 1:05
Differential - Input:Output Yes/Yes
Frequency - Max 1.4GHz
Divider/Multiplier Yes/No
Voltage - Supply 3.15 V ~ 5.25 V
Operating Temperature -40°C ~ 105°C
Mounting Type Surface Mount
Package / Case 48-WFQFN Exposed Pad
Supplier Device Package 48-QFN (5x9)

LTC6950IUHH Features

● Low Phase Noise and Jitter
● Additive Jitter: 18fsRMS (12kHz to 20MHz)
● Additive Jitter: 85fsRMS (10Hz to Nyquist)
● EZSync™ Multichip Clock Edge Synchronization
● Full PLL Core with Lock Indicator
● –226dBc/Hz Normalized In-Band Phase Noise Floor
● –274dBc/Hz Normalized 1/f Phase Noise
● 1.4GHz Maximum VCO Input Frequency
● Four Independent, Low Noise 1.4GHz LVPECL Outputs
● One LVDS/CMOS Configurable Output
● Five Independently Programmable Dividers Covering All Integers from 1 to 63
● Five Independently Programmable VCO Clock Cycle Delays Covering All Integers from 0 to 63
● –40°C to 105°C Junction Temperature Range

LTC6950IUHH Applications

● Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems
● Low Jitter Clock Generation and Distribution

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LTC6950IUHH Description

The LTC6950IUHH is a low phase noise integer-N frequency synthesizer core with clock distribution. The LTC6950IUHH delivers the low phase noise clock signals demanded in high frequency, high resolution data acquisition systems.

The frequency synthesizer contains a full low noise PLL core with a programmable reference divider (R), a programmable feedback divider (N), a phase/frequency detector (PFD) and a low noise charge pump (CP). The clock distribution section of the LTC6950 delivers up to five outputs based on the VCO input. Each output is individually programmed to divide the VCO input frequency by any integer from 1 to 63 and to delay the output by 0 to 63 VCO clock cycles. Four of the outputs feature very low noise, low skew LVPECL logic signals capable of operation up to 1.4GHz. The fifth output is selectable as either an LVDS (800MHz) or CMOS (250MHz) logic type. This output is also programmed to produce an output signal based on either the VCO input or the reference divider output.

LTC6950IUHH Tags

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